San Mateo, Calif. – InTime Software Inc. will unveil a register-transfer-level timing tool this week intended to help IC designers develop timing-accurate RTL code before they move to synthesis, ...

SAN MATEO, Calif. — Static timing analysis is one of the pilings upon which the whole edifice of modern IC design has been erected. But this vital technique itself rests upon assumptions that may no ...

Magma's Tekton static timing analyzer is a next-generation tool built to handle the exploding number of STA scenarios required in modern SoC design. Static timing analysis (STA) is used throughout ...

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address ...

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...

Statistical static timing analysis (SSTA) offers a number of advantages over traditional corner based static timing analysis. Most notably, it provides a more realistic estimation of timing relative ...

As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, ...

Achieving timing closure in system-on-a-chip designs in a reasonable amount of time can be daunting. You can wait until you get to the block-level integration stage, but you'll probably have an easier ...

Cadence has announced a design tool for IC design sign-off. Called Certus closure solution, the “environment automates and accelerates the complete design closure cycle, from sign-off optimisation ...